Digital data transmitting apparatus

ABSTRACT

A transmitting circuit  10  converts transmission data to a multilevel analog signal suitable for transmission. The multilevel analog signal is output to a cable  21  via an amplifier and a hybrid circuit  12 . In the transmitting circuit  10 , a waveform which compensates waveform deterioration at the cable  21  is generated. A reception signal from the cable  21  is input to a mixer  14  via the hybrid circuit  12  and an amplifier  13 . The mixer  14  mixes the reception signal and a cancel signal output from a cancel signal generation circuit  17  so as to remove undesired signals. In a receiving circuit  15 , the signal output from the mixer  14  is sampled by use of a plurality of sample-hold circuits, and subjected to analog sum-of-product computation which is performed by a matrix circuit for distortion compensation. Subsequently, the sampled signals are converted to digital signals. The digital signals are collectively subjected to processing such as parallel-serial conversion, whereby reception data and an evaluation signal are obtained. An adjustment control circuit  18  includes a CPU, and adjusts the respective circuits on the basis of the evaluation signal such that data can be correctly transmitted and received.

This application claims the benefit of PCT International ApplicationNumber PCT/JP2004/012970 filed Sep. 7, 2004 and Japanese Application No.2003-317638, filed Sep. 10, 2003, in Japan, the disclosures of which areincorporated herein by reference.

TECHNICAL FIELD

The present invention relates to an apparatus for transmitting digitaldata via a signal cable. In particular, the present invention relates toa transmission apparatus suitable for data transmission at high speed of1 giga bits per sec or higher.

BACKGROUND ART

In general, in a hybrid circuit, which is used in the case where digitaldata are transmitted by use of a signal cable for bidirectionalcommunications, a transmission signal and a reception signal areseparated from each other by means of a high-frequency transformer.Moreover, when a signal is transmitted through a cable, the signalwaveform deteriorates considerably. Therefore, a digital signalprocessing (DSP) technique has been conventionally used in order toobtain accurate reception data.

In a conventional digital data transmission apparatus as describedabove, the highest communication speed is 250 mega bits per sec percommunication channel, as in the case of a 1000 mega-bit ethernet asdisclosed in the following Non-Patent Document 1. Therefore, high-speeddata transmission of 1 giga bits per sec per communication channel orhigher has been impossible.

The reasons for the impossibility of high-speed data transmission of 1giga bits per sec or higher are as follows. That is, at frequencies ofsignals used for high-speed communications, signal separation by use ofa high-frequency transformer is very difficult; and an analog-digitalconverter (A/D converter) and a digital processing circuit, which areused for digital signal processing (DSP), are not practical in terms ofoperation speed, circuit size, power consumption, and cost.

-   Non-Patent Document 1: IEEE802.3ab Specifications    http://grouper.ieee.org/groups/802/3/ab/

DISCLOSURE OF THE INVENTION

Problems to be Solved by the Invention

An object of the present invention is to solve the above-describedproblems of the conventional technique and to provide a high-speed datatransmission apparatus capable having a transmission speed of 1 gigabits per sec per communication channel or higher.

Means for Solving the Problems

The present invention provides a digital data transmission apparatus ofa multilevel transmission scheme, comprising transmitting meansincluding an adjustable preemphasis circuit; receiving means includingevaluation-signal generation means for generating an evaluation signalregarding an adjusted condition from a received signal; and adjustmentmeans for adjusting the receiving means or transmitting means of acounterpart apparatus by use of the evaluation signal.

The digital data transmission apparatus may further comprise a hybridcircuit which can perform balance adjustment by means of a resistormatrix circuit; and the receiving means may further include anadjustable echo cancel circuit.

In the digital data transmission apparatus, the evaluation-signalgeneration means may be configured to determine whether the level of thereceived signal is in the vicinity of the center of a corresponding oneof determination ranges corresponding to multi levels or in the vicinityof a boundary thereof and output histogram information representing itsfrequency; and the adjustment means may adjust a preemphasis circuit ofthe counterpart apparatus. In the digital data transmission apparatus,the adjustment means may adjust the respective circuits by means of agenetic algorithm.

In the digital data transmission apparatus, the receiving means mayfurther include an adjustable distortion elimination circuit whichperforms analog processing for the received signal. In the digital datatransmission apparatus, the receiving means may further include a clockregeneration circuit in which a voltage-controlled variable crystaloscillation circuit is used as a voltage-controlled oscillator of aphase-locked loop circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

[FIG. 1] Block diagram showing the configuration of a full-duplextransmitting receiving circuit of the present invention.

[FIG. 2] Block diagram showing the configuration of an entiretransmission apparatus of the present invention.

[FIG. 3] Block diagram showing the configuration of a transmittingcircuit of the present invention.

[FIG. 4] Circuit diagram showing the configuration of a hybrid circuit12 of the present invention.

[FIG. 5] Block diagram showing the configuration of a cancel signalgeneration circuit of the present invention.

[FIG. 6] Block diagram showing the configuration of a receiving circuit15 of the present invention.

[FIG. 7] Waveform charts showing waveforms observed in the transmittingcircuit 10 for the case of a single pulse.

[FIG. 8] Waveform charts showing waveforms observed in the transmittingcircuit 10 for the case of continuous data transmission.

[FIG. 9] Block diagram showing the configuration of an evaluation-signalgenerating circuit of the present invention.

[FIG. 10] Flowchart showing the contents of adjustment processing of thepresent invention.

[FIG. 11] Block diagram showing the configuration of a matrix circuit ofthe present invention.

[FIG. 12] Block diagram showing a main portion of a clock regenerationcircuit of the present invention.

DESCRIPTION OF REFERENCE NUMERALS

-   10: transmitting circuit-   11, 13: amplifier-   12: hybrid circuit-   21: cable-   22: counterpart apparatus-   14: adder-   15: receiving circuit-   16: clock regeneration circuit-   17: cancel signal generation circuit-   18: adjustment control circuit

BEST MODE FOR CARRYING OUT THE INVENTION

A digital data transmission apparatus which can perform full-duplextransmission at a total speed of 10 giga bits per sec (Gbps) in a pulseamplitude modulation (PAM) scheme by use of four coaxial cables willnext be described.

Embodiment 1

An embodiment of the present invention will now be described in details.FIG. 1 is a block diagram showing the configuration of a full-duplextransmitting receiving circuit 20 of the present invention. FIG. 2 is ablock diagram showing the configuration of an entire transmissionapparatus of the present invention. This apparatus transmits digitaldata, which are mainly handled in a computer, to another computer, anexternal device, a network, or the like.

The transmission apparatus of the present invention is connected, via acable 21, with a counterpart transmission apparatus 22 having the sameconfiguration. In the present invention, the cable 21 preferably has acoaxial structure rather than a twist-pair wire structure. Fortransmission of a plurality of (e.g., 4) channels, a composite coaxialcable in which a plurality of coaxial cables are bound is preferablyused. In this case, no problem arises even when the outer conductor ofeach coaxial cable comes into contact with the outer conductors ofother, co-bound coaxial cables. In this case, the outer diameter of thecomposite coaxial cable can be reduced.

The transmission apparatus includes four full-duplex transmittingreceiving circuits 20, a data distribution circuit 23, and a data mixingcircuit 24. The data distribution circuit 23 divides transmission datainto data segments of, for example, 8-bit length, and converts them todata segments each including 12 bits in total and composed of four 3-bitdata segments which correspond to four-channel, five-level pluses andfor which error detection correction is possible, and distributescorresponding three bits of each 12-data segment to each of the fourfull-duplex transmitting receiving circuits 20. The data mixing circuit24 reproduces the original 8-bit data segments from the 12-bit datasegments each composed of four 3-bit data segments corresponding tofour-channel, five-level pluses. Notably, the number of transmissionlevels in multilevel transmission is not limited to 5, and the number oflevels may be 8 or 12.

The configuration of each full-duplex transmitting receiving circuit 20will now be described. Transmission data are converted by a transmittingcircuit 10 to a multilevel analog signal suitable for transmission. Themultilevel analog signal is amplified by means of an amplifier 11 to alevel suitable for transmission, and then output to the cable 21 via ahybrid circuit 12. In the transmitting circuit 10, a waveform whichcompensates waveform deterioration at the cable 21 is generated in amanner described below.

A portion of the transmission signal becomes an undesired signal called“echo” because of reflection at a connection point or the like presenton the cable 21. For accurate data transmission, such an undesiredsignal must be properly removed. A reception signal from the cable 21 isseparated from the transmission signal by means of the hybrid circuit12, and is fed to an amplifier 13. A cancel signal generation circuit 17generates, from the transmission data, a cancel signal for eliminatingthe undesired signal.

The reception signal output from the amplifier 13 and the cancel signaloutput from the cancel signal generation circuit 17 are mixed by meansof a mixer 14, whereby the undesired signal is removed. As will bedescribed in detail, in the receiving circuit 15, the output signal ofthe mixer 14 is sampled by use of a plurality of sample-hold circuits,and analog sum-of-product computation is performed by a matrix circuitso as to correct distortion. The thus-obtained distortion-free analogsignals are converted to digital signals by use of analog-digitalconverters. The thus-obtained digital signals are collectively subjectedto processing such as parallel-serial conversion in a logic circuit.Thus, reception data and an evaluation signal to be described later areobtained.

For determining timings of the above-described series of operations, aclock regeneration circuit 16 extracts a clock signal, from whichvarious timing signals are generated. An adjustment control circuit 18includes a CPU, and adjusts the respective circuits on the basis of theevaluation signal such that data can be correctly transmitted andreceived, as will be described in detail.

Notably, the transmission line 21 may be used as a unidirectionaltransmission line rather than a full-duplex transmission line. In thiscase, the output of the amplifier 11 is connected directly to a cable 21for transmission, and a cable 21 for reception is connected to theamplifier 13. The hybrid circuit 12, the cancel signal generationcircuit 17, and the mixer 14 become unnecessary.

FIG. 3 is a block diagram showing the configuration of the transmittingcircuit 10 of the present invention. D/A converters DAC1 (32) to DAC3(34) are of a differential current output type. The outputs of the D/Aconverters DAC1 to DAC3 are connected in parallel such that thepolarities of the outputs of the D/A converter DAC1 become reverse tothose of the outputs of the D/A converter DAC3 and equal to those of theoutputs of the D/A converter DAC2. Transmission data and a clock signalare fed to the D/A converter DAC1 as they are. The transmission data andthe clock signal are fed to the D/A converter DAC2 with a delay of apredetermined time (Td1) produced by a delay circuit 30. Thetransmission data and the clock signal are fed to the D/A converter DAC3with a delay of a predetermined time (Td1+Td2) produced by the delaycircuit 30 and a delay circuit 31. Notably, the Td1 and Td2 may beadjusted by means of the adjustment control circuit 18.

FIG. 7 is a set of waveform charts showing waveforms observed in thetransmitting circuit 10 in the case where a single pulse is transmitted.FIG. 8 is a set of waveform charts showing waveforms observed in thetransmitting circuit 10 in the case where continuous data aretransmitted. The waveforms in each set show transmission data (digitaldata), the outputs (current values) of the DAC1 to DAC3, and the output(current value) of the transmitting circuit 10, respectively (all thewaveforms were obtained through a computer simulation). The DAC1 to DAC3are configured such that the magnification of output current can bevaried through variation of their bias currents. When the outputcurrents of the DAC1 to DAC3 are assumed to be at levels a1, a2, and a3,respectively, when the transmission data are “1,” the output waveform ofthe transmitting circuit 10 becomes a preemphasis waveform as shown inthe lowest section of FIG. 7. The values of a1, a2, and a3 are adjustedby means of the adjustment control circuit 18 such that a preemphasiswaveform suitable for the cable is obtained.

FIG. 4 is a circuit diagram showing the configuration of the hybridcircuit 12 of the present invention. A connector 57 connected to theabove-described cable 21 is connected to a resistor matrix circuit 58composed of resistors 42 to 51. The resistor matrix circuit 58 isconnected to high-frequency transformers 41, 52, and 53. The resistanceof the resistor 46 is equal to the characteristic impedance of the cable21, which is connected to the connector 57.

The output of the amplifier 11 is connected to the primary winding ofthe high-frequency transformer 41. The transmission signal is amplifiedby the amplifier 11, and then output to the high-frequency transformer41. One end of the secondary winding of the high-frequency transformer41 is connected to the connector 57 and the resistor 47 via the resistor42. The other end of the secondary winding of the high-frequencytransformer 41 is connected to the resisters 46 and 49 via the resistor45. The transmission signal is fed in opposite phases (in the form ofvoltages of opposite polarities) to the node (called node N1) where theconnector 57, the resistor 42, and the resistor 47 are connectedtogether and the node (called node N2) where the resistor 46, theresistor 45, and the resistor 49 are connected together, respectively.

The resistor 47 is connected to the primary winding of thehigh-frequency transformer 52, and the resistor 49 is connected to theprimary winding of the high-frequency transformer 53. Therefore, thecomponents of the transmission signal appear in opposite phases from thesecondary windings of the high-frequency transformers 52 and 53.

The reception signal from the connector 57 is fed to the primary windingof the high-frequency transformer 52 via the resistor 47, and is fed tothe primary winding of the high-frequency transformer 53 via theresistors 47 and 48. Therefore, the components of the reception signalappear in the phase (in the form of voltages of the same polarity) fromthe secondary windings of the high-frequency transformers 52 and 53.

The secondary windings of the high-frequency transformers 52 and 53 areconnected to amplifiers 54 and 55, respectively. The outputs of theamplifiers 54 and 55 are mixed through addition, whereby the receptionsignal is obtained. At this time, the components of the transmissionsignal are mixed in opposite phases, whereby the reception signal isseparated from the transmission signal. The resistors 43, 44, 50, and 51are used for impedance matching.

Because of variations in the characteristic impedance of the cable 21and the resistance of the resistor 46, the magnitudes of theopposite-phase components of the transmission signal output from theamplifiers 54 and 55 are not necessarily the same. In view of this,through adjustment of the amplification factors of the amplifiers 54 and55, the components of the transmission signal can be removed from thereception signal. The amplification factors are optimized by means ofthe adjustment control circuit 18 in accordance with a geneticalgorithm.

As described above, the characteristic feature of the hybrid circuit 12of the present invention resides in that the amplifiers 54 and 55provide two signal paths, and the balance between the signals outputfrom the two signal paths is adjusted.

FIG. 5 is a block diagram showing the configuration of the cancel signalgeneration circuit 17 of the present invention. Transmission data areinput to shift registers 60 connected in cascade, whereby thetransmission data are successively and temporarily stored in shiftregisters 60. The outputs of the shift registers are fed to a selector61, which selects a portion of the record of the transmission data. Theoutputs of the selector 61 are converted to analog currents by means ofa plurality of D/A converters 62. All the outputs of the D/A converters62 are connected in parallel so as to mix the currents through addition,to thereby generate a cancel signal. The selector 61 (tap position) andthe currents (polarities and amplitudes) output from the DAC 62 areadjusted by means of the adjustment control circuit 18.

FIG. 6 is a block diagram showing the configuration of a receivingcircuit 15 of the present invention. In the receiving circuit 15, theoutput signal of the mixer 14 is sampled by means of a plurality ofsample-hold (S/H) circuits 70. In order to cause a plurality of ADCs 73to effect parallel operation in sequence, the S/H circuits 70 operate insequence, one at a time, at timings determined on the basis of the clocksignal. The timings are adjusted by means of the adjustment controlcircuit 18. In order to remove distortion, signals output from the S/Hcircuits 70 are subjected to analog sum-of-product computation performedby a matrix circuit 71.

FIG. 11 is a block diagram showing the configuration of the matrixcircuit 71 of the present invention. A signal output from one variablegain amplifier 75 and signals output from two variable gain, variablepolarity amplifiers 76 are added by means of an analog adder 77, and asignal obtained as a result of addition is output. The gain and polarityof each amplifier are adjusted by means of the adjustment controlcircuit 18.

The outputs of the matrix circuit 71 are amplified by a plurality ofamplifiers 72 to a level suitable for analog to digital conversion. Theamplified outputs are converted to digital signals by means of theanalog digital converters 73. In the case where distortion of thewaveforms of the reception signal is small, the matrix circuit 71 may beomitted. In this case, the outputs of the S/H circuits 70 are connecteddirectly to the amplifiers 72. The digital signals output from theanalog digital converters 73 are collectively subjected to processingsuch as parallel-serial conversion in a logic circuit 74, wherebyreception data and an evaluation signal are obtained.

FIG. 12 is a block diagram showing a main portion of the clockregeneration circuit of the present invention. In order to reproducereception data from the reception signal, a clock signal correspondingto the received data must be regenerated. In the case of multilevelsignals, clock regeneration is difficult. However, through trial anderror, the present inventor found that the clock regeneration circuit 16operates well when a voltage-controlled variable crystal oscillationcircuit is used as a voltage-controlled variable oscillator used in aphase-locked loop (PLL) circuit.

A reception signal 101 is converted to a binary signal by means of acomparator, and the binary signal is fed to a synchronous patterndetection circuit 103 and a PLL (phase-locked loop) circuit 104. Thedetection output of the synchronous pattern detection circuit isconnected to an enable terminal of the PLL circuit 104. The output ofthe PLL circuit 104 is connected to a voltage-controlled oscillator 105.The output of the voltage-controlled oscillator 105 is output, as aclock signal, to the PLL circuit and to the outside. The PLL circuit 104and the voltage-controlled oscillator 105 undergo synchronizationpull-in control only during periods in which a synchronization patternis detected, and enter in a free-run state in the remaining periods.Through use of a voltage-controlled variable crystal oscillation circuitfor the voltage-controlled oscillator 105, stable synchronization of theclock signal becomes possible.

FIG. 9 is a block diagram showing the configuration of anevaluation-signal generating circuit of the present invention. FIG. 9schematically shows the results of determination performed by the A/Dconverter 73 so as to determine digital values from the level of ananalog signal. If a digital value, which is one of five values; i.e.,“+2,” “+1,” “0,” “−1,” and “−2,” can be determined from the level of theanalog signal, digital data can be obtained. The error rate of thereceived multilevel analog signal changes as follows. The closer thelevel of the signal to the center of a determination range for thecorresponding level, the lower the error rate; and the closer the levelof the signal to the upper or lower threshold of the determinationrange, the higher the error rate. In view of the above, thedetermination range for each of five values is divided into subranges soas to distinguish the case where the level of the analog signal is nearthe center of the corresponding determination range from the case wherethe level of the analog signal is near the threshold thereof, which isthe boundary of the determination range.

The input signal is input to the “+” terminal of each comparator 80, anda threshold voltage to be compared with the input signal is input to the“−” terminal of each comparator 80. Three comparators 80 are providedfor each of multilevel determination ranges. The three comparators 80for each determination range are applied with voltages (thresholdvoltages) which correspond to the lower limit level, a level one-third(of the determination range) higher than the lower limit level, and alevel two-thirds higher than the lower limit level (one-third lower thanthe upper limit level), respectively. Only comparators which havedetermined that the corresponding threshold signal is lower than theinput signal output “1,” which is stored in a corresponding latch 81.

Since one input of each AND gate 83 is connected with the output of alatch on the upper row via a NOT gate 82, only when the output of theupper row latch is “1,” the output of the AND gate 83 becomes “0.” As aresult, only the AND gate 83 which corresponds to the threshold valuewhich is lower than the input signal and closest thereto outputs “1.” InFIG. 9, a determination output signal marked with “◯” represents thatthe level of the analog signal is in the vicinity of the center of thecorresponding determination range; and a determination output signalmarked with “Δ” represents that the level of the analog signal is in thevicinity of the corresponding threshold. OR gates 85 to 89 eachcalculate a logical sum of outputs of AND gates belonging to each of themultilevel determination ranges, to thereby output multilevel data. Abinary converter 90 converts the multilevel data to binary data.

In a predetermined period, the number of determination “◯” outputsignals and the number of determination “Δ” output signals in the A/Dconverter 73 are counted by use of OR gates 92 and 93 and histogramcounters 94 and 95, and histogram data, representing frequencies, areoutput. The histogram data are output to the adjustment control circuit18 as an evaluation signal.

Through use of a genetic algorism, the adjustment control circuit 18adjusts the amplification factors of the amplifiers 54 and 55 in thehybrid circuit 12, the output waveform of the cancel signal generationcircuit 17, the coefficients of the analog sum-of-product computation atthe matrix circuit 71, etc. Further, the adjustment control circuit 18transmits to the counterpart apparatus adjustment parameters regardingthe transmitting circuit of the counterpart apparatus, and adjusts thelevel parameters, etc. of the preemphasis circuit of the transmittingcircuit of the counterpart apparatus.

Next, a method of adjusting the circuit by use of a genetic algorismwill be described. Notably, an example reference regarding a geneticalgorism is “Genetic Algorithms in Search, Optimization, and MachineLearning” written by David E. Goldberg and published in 1989 byADDISON-WESLEY PUBLISHING COMPANY, INC. Notably, the term “geneticalgorithm” used herein refers to an evolutionary computation method,including an evolutionary programming (EP) method. An example referenceregarding evolutionary programming is “Evolutionary Computation: Towarda New Philosophy of Machine Intelligence” written by D. B. Fogel andpublished in 1995 by IEEE Press.

The length of the cable 21 connected to the transmission apparatus 1,the position of an intermediate connection point, characteristicimpedance, frequency characteristic, etc. change, for example, uponreplacement of the cable. Therefore, the waveform of the transmissionsignal generated in the transmitting circuit 10, the output waveform ofthe cancel signal generation circuit 17, the amplification factors ofthe amplifiers 54 and 55 in the hybrid circuit 12, the coefficients ofthe analog sum-of-product computation at the matrix circuit 71, etc.must be optimally adjusted in accordance with the characteristics of thecable 21. The genetic algorithm is particularly suitable for thisadjustment. Since a specific adjustment procedure is described in detailin Japanese Patent Application Laid-Open (kokai) No. 2000-156627(“Electronic Circuit and Method of Adjusting the Same”), its outlinewill be described here.

In the adjustment procedure, first, at the time of startup of theapparatus, low-speed data communication is established betweentransmitting receiving circuits by use of a protocol which enablescommunications in an unadjusted condition; e.g., through decreasing thenumber of signal levels or the transmission speed. Subsequently, thetransmitting side is caused to send a training signal, and an evaluationsignal is obtained on the receiving side. On the basis of the evaluationsignal, the adjustment control circuit 18 adjusts the receiving circuitby use of a genetic algorithm. Further, via a low-speed datacommunication channel, the adjustment control circuit 18 transmits tothe counterpart apparatus adjustment parameters of the transmittingcircuit of the counterpart apparatus, to thereby adjust the transmittingcircuit of the counterpart apparatus. After adjustment has beenperformed within a relatively wide adjustment range through thistraining processing, high-speed data communication is establishedbetween the transmission apparatuses. After that, while actual datatransmission is being performed, on-line fine adjustment is performedsuch that the transmission apparatuses are maintained in optimalconditions. The range of adjustment during transmission is limited to anarrow range around the favorable point attained through the immediatelyprevious adjustment, so as not to impose a large influence on thequality of communications between the transmission apparatuses. Duringthe on-line adjustment, the evaluation function of the genetic algorithmutilizes the results of signal determination in the A/D converter 73(evaluation signal).

FIG. 10 is a flowchart showing the outline of adjustment processing ofthe present invention. In S10, initialization is performed. In S11,genes of individuals of an initial population are generated, centeringon a site having a high evaluation value. In the present embodiment, theregister values of registers which store adjustment values are directlyused as chromosomes of the genetic algorithm. In S12, a fitness of eachindividual is generated. That is, for each individual whose evaluationvalue has not yet been measured, adjustment values of the individual areset to the circuit, a signal is transmitted for a predetermined periodof time, and the above-mentioned evaluation signal is obtained. Theevaluation function value F of the genetic algorithm is calculated bythe following equation, for example.F=(the number of ◯)/((the number of ◯)+(the number of Δ))

Here, the number of ◯ is the count value of the histogram counter 95 atthe end of the predetermined period, and the number of Δ is the countvalue of the histogram counter 94 at the end of the predeterminedperiod. In S13, selection of individuals is performed. That is,individuals are sorted in the order of their evaluation values, and apredetermined number of individuals at the bottom are removed. In S14,gene crossover is effected. Specifically, a predetermined number ofpairs of individuals are randomly selected (copied), and theirchromosomes are exchanged so as to produce offspring genes.

In S15, mutation is effected where a predetermined number of individualsare randomly selected (copied), and their genes are modified so as togenerate a new individual. In S16, determination as to whether or notthe evaluation criteria are satisfied; i.e., whether or not the bestevaluation function value F is equal to or grater than the predeterminedvalue, is performed. When the evaluation criteria are satisfied, theprocessing is ended. When the evaluation criteria are not satisfied, theprocessing is repeated after returning to S12. When the processing isended, the individual having the highest fitness among the biologicalpopulation at that time is considered the solution of the optimizationproblem to be obtained. In the above-described manner, the transmissionapparatus is automatically adjusted on line such that consistentcommunication quality is attained.

1. A digital data transmission apparatus of a multilevel transmissionscheme, comprising: transmitting means including an adjustablepreemphasis circuit; receiving means including evaluation-signalgeneration means for generating an evaluation signal regarding anadjusted condition from a received signal; adjustment means foradjusting the receiving means or transmitting means of a counterpartapparatus by use of the evaluation signal; and a hybrid circuit whichcan perform balance adjustment by means of a resistor matrix circuit,wherein the receiving means further includes an adjustable echo cancelcircuit.
 2. A digital data transmission apparatus of a multileveltransmission scheme, comprising: transmitting means including anadjustable preemphasis circuit; receiving means includingevaluation-signal generation means for generating an evaluation signalregarding an adjusted condition from a received signal; and adjustmentmeans for adjusting the receiving means or transmitting means of acounterpart apparatus by use of the evaluation signal, wherein theevaluation-signal generation means is configured to determine whetherthe level of the received signal is in the vicinity of the center of acorresponding one of determination ranges corresponding to multi levelsor in the vicinity of a boundary thereof and output histograminformation representing its frequency; and the adjustment means adjustsa preemphasis circuit of the counterpart apparatus.
 3. A digital datatransmission apparatus of a multilevel transmission scheme, comprising:transmitting means including an adjustable preemphasis circuit;receiving means including evaluation-signal generation means forgenerating an evaluation signal regarding an adjusted condition from areceived signal; and adjustment means for adjusting the receiving meansor transmitting means of a counterpart apparatus by use of theevaluation signal, wherein the adjustment means adjusts respectivecircuits by means of a genetic algorithm.
 4. A digital data transmissionapparatus of a multilevel transmission scheme, comprising: transmittingmeans including an adjustable preemphasis circuit; receiving meansincluding evaluation-signal generation means for generating anevaluation signal regarding an adjusted condition from a receivedsignal; and adjustment means for adjusting the receiving means ortransmitting means of a counterpart apparatus by use of the evaluationsignal, wherein the receiving means further includes an adjustabledistortion elimination circuit which performs analog processing for thereceived signal.
 5. A digital data transmission apparatus of amultilevel transmission scheme, comprising: transmitting means includingan adjustable preemphasis circuit; receiving means includingevaluation-signal generation means for generating an evaluation signalregarding an adjusted condition from a received signal; and adjustmentmeans for adjusting the receiving means or transmitting means of acounterpart apparatus by use of the evaluation signal, wherein thereceiving means further includes a clock regeneration circuit in which avoltage-controlled variable crystal oscillation circuit is used as avoltage-controlled oscillator of a phase-locked loop circuit.